Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms

Design&Test
2004
Issue No. 5 - September/October
Abstract - Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms

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September/October 2004 (vol. 21 no. 5)

pp. 368-377

	ASCII Text	x
	Alexander Maxiaguine, Samarjit Chakraborty, Simon K?, Lothar Thiele, "Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms," IEEE Design and Test of Computers, vol. 21, no. 5, pp. 368-377, September/October, 2004.

	BibTex	x
	@article{ 10.1109/MDT.2004.60, author = {Alexander Maxiaguine and Samarjit Chakraborty and Simon K? and Lothar Thiele}, title = {Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms}, journal ={IEEE Design and Test of Computers}, volume = {21}, number = {5}, issn = {0740-7475}, year = {2004}, pages = {368-377}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.60}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms IS - 5 SN - 0740-7475 SP368 EP377 EPD - 368-377 A1 - Alexander Maxiaguine, A1 - Samarjit Chakraborty, A1 - Simon K?, A1 - Lothar Thiele, PY - 2004 VL - 21 JA - IEEE Design and Test of Computers ER -

Alexander Maxiaguine, Swiss Federal Institute of Technology

Samarjit Chakraborty, National University of Singapore

Simon K?, Swiss Federal Institute of Technology

Lothar Thiele, Swiss Federal Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.60

Editors' note:Scheduling on-chip resources using analytical techniques is becoming increasingly important in multimedia processing. This article presents an analytical framework for designing and evaluating schedulers for SoC multimedia platforms. The modeling technique subsumes standard event models used in real-time scheduling and accurately captures the variability in task execution requirements.

--Radu Marculescu, Carnegie Mellon University; and Petru Eles, Linköping University

Citation:

Alexander Maxiaguine, Samarjit Chakraborty, Simon K?, Lothar Thiele, "Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms," IEEE Design and Test of Computers, vol. 21, no. 5, pp. 368-377, Sep./Oct. 2004, doi:10.1109/MDT.2004.60

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