Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects

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	Similar Articles Articles by Nelson Ou Articles by Touraj Farahmand Articles by Andy Kuo Articles by Sassan Tabatabaei Articles by Andr? Ivanov

July/August 2004 (vol. 21 no. 4)

pp. 302-313

	ASCII Text	x
	Nelson Ou, Touraj Farahmand, Andy Kuo, Sassan Tabatabaei, Andr? Ivanov, "Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects," IEEE Design and Test of Computers, vol. 21, no. 4, pp. 302-313, July/August, 2004.

	BibTex	x
	@article{ 10.1109/MDT.2004.34, author = {Nelson Ou and Touraj Farahmand and Andy Kuo and Sassan Tabatabaei and Andr? Ivanov}, title = {Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects}, journal ={IEEE Design and Test of Computers}, volume = {21}, number = {4}, issn = {0740-7475}, year = {2004}, pages = {302-313}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.34}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects IS - 4 SN - 0740-7475 SP302 EP313 EPD - 302-313 A1 - Nelson Ou, A1 - Touraj Farahmand, A1 - Andy Kuo, A1 - Sassan Tabatabaei, A1 - Andr? Ivanov, PY - 2004 VL - 21 JA - IEEE Design and Test of Computers ER -

Nelson Ou, University of British Columbia

Touraj Farahmand, University of British Columbia

Andy Kuo, University of British Columbia

Sassan Tabatabaei, University of British Columbia

Andr? Ivanov, University of British Columbia

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.34

Gigabit data rates in high-speed interconnects require careful modeling of jitter and its effect on the bit error rates. This article presents a comprehensive analysis of jitter causes and types, and develops accurate jitter models for design and test of high-speed interconnects.

Citation:

Nelson Ou, Touraj Farahmand, Andy Kuo, Sassan Tabatabaei, Andr? Ivanov, "Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects," IEEE Design and Test of Computers, vol. 21, no. 4, pp. 302-313, July/Aug. 2004, doi:10.1109/MDT.2004.34

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