Understanding Yield Losses in Logic Circuits

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	Similar Articles Articles by Davide Appello Articles by Alessandra Fudoli Articles by Katia Giarda Articles by Vincenzo Tancorre Articles by Emil Gizdarski Articles by Ben Mathew

May/June 2004 (vol. 21 no. 3)

pp. 208-215

	ASCII Text	x
	Davide Appello, Alessandra Fudoli, Katia Giarda, Vincenzo Tancorre, Emil Gizdarski, Ben Mathew, "Understanding Yield Losses in Logic Circuits," IEEE Design and Test of Computers, vol. 21, no. 3, pp. 208-215, May/June, 2004.

	BibTex	x
	@article{ 10.1109/MDT.2004.21, author = {Davide Appello and Alessandra Fudoli and Katia Giarda and Vincenzo Tancorre and Emil Gizdarski and Ben Mathew}, title = {Understanding Yield Losses in Logic Circuits}, journal ={IEEE Design and Test of Computers}, volume = {21}, number = {3}, issn = {0740-7475}, year = {2004}, pages = {208-215}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.21}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Understanding Yield Losses in Logic Circuits IS - 3 SN - 0740-7475 SP208 EP215 EPD - 208-215 A1 - Davide Appello, A1 - Alessandra Fudoli, A1 - Katia Giarda, A1 - Vincenzo Tancorre, A1 - Emil Gizdarski, A1 - Ben Mathew, PY - 2004 VL - 21 JA - IEEE Design and Test of Computers ER -

Davide Appello, STMicroelectronics

Alessandra Fudoli, STMicroelectronics

Katia Giarda, STMicroelectronics

Vincenzo Tancorre, STMicroelectronics

Emil Gizdarski, Synopsys

Ben Mathew, Synopsys

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.21

Yield improvement requires understanding failures and identifying potential sources of yield loss. This article focuses on diagnosing random logic circuits and classifying faults. The authors introduce an interesting scan-based diagnosis flow, which leverages the ATPG patterns originally generated for fault coverage. This flow shows an adequate link between the design automation tools and the testers, and a correlation between the ATPG patterns and the tester failure reports.

Citation:

Davide Appello, Alessandra Fudoli, Katia Giarda, Vincenzo Tancorre, Emil Gizdarski, Ben Mathew, "Understanding Yield Losses in Logic Circuits," IEEE Design and Test of Computers, vol. 21, no. 3, pp. 208-215, May/June 2004, doi:10.1109/MDT.2004.21

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