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Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification
March/April 2004 (vol. 21 no. 2)
pp. 84-93
ASCII Text
x 
 
Allon Adir, Eli Almog, Laurent Fournier, Eitan Marcus, Michal Rimon, Michael Vinov, Avi Ziv, "Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification," IEEE Design and Test of Computers, vol. 21, no. 2, pp. 84-93, March/April, 2004.
 
 
BibTex
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@article{ 10.1109/MDT.2004.1277900,
author = {Allon Adir and Eli Almog and Laurent Fournier and Eitan Marcus and Michal Rimon and Michael Vinov and Avi Ziv},
title = {Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification},
journal ={IEEE Design and Test of Computers},
volume = {21},
number = {2},
issn = {0740-7475},
year = {2004},
pages = {84-93},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.1277900},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification
IS - 2
SN - 0740-7475
SP84
EP93
EPD - 84-93
A1 - Allon Adir,
A1 - Eli Almog,
A1 - Laurent Fournier,
A1 - Eitan Marcus,
A1 - Michal Rimon,
A1 - Michael Vinov,
A1 - Avi Ziv,
PY - 2004
VL - 21
JA - IEEE Design and Test of Computers
ER -
 
Allon Adir, IBM Research Lab, Haifa
Eli Almog, IBM Research Lab, Haifa
Laurent Fournier, IBM Research Lab, Haifa
Eitan Marcus, IBM Research Lab, Haifa
Michal Rimon, IBM Research Lab, Haifa
Michael Vinov, IBM Research Lab, Haifa
Avi Ziv, IBM Research Lab, Haifa
Historically, IBM's random test-program generation (RTPG) methodology has tightly coupled architectural information with the TPG tool. Model-based TPG removes this architecture dependency and provides a generic solution to functional testbench generation. Genesys-Pro, the second-generation model-based TPG tool, has many improvements over its predecessor, Genesys, including greater expressive power in the test template language and more constraint-solving processing power.
Citation:
Allon Adir, Eli Almog, Laurent Fournier, Eitan Marcus, Michal Rimon, Michael Vinov, Avi Ziv, "Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification," IEEE Design and Test of Computers, vol. 21, no. 2, pp. 84-93, Mar./Apr. 2004, doi:10.1109/MDT.2004.1277900
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