With today's rapidly shrinking process geometries, designers must address crosstalk, electromigration, IR drop, and other effects earlier in the design cycle to achieve signal integrity. The authors present a new placement algorithm that minimizes crosstalk and increases design speed 8% on average, in comparison with a traditional timing-driven, congestion-aware placement flow.
Citation:
Jinan Lou, Wei Chen, "Crosstalk-Aware Placement," IEEE Design and Test of Computers, vol. 21, no. 1, pp. 24-32, Jan./Feb. 2004, doi:10.1109/MDT.2004.1261847 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||