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An Integrated Environment for Technology Closure of Deep-Submicron IC Designs
January/February 2004 (vol. 21 no. 1)
pp. 14-22
ASCII Text
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Louise Trevillyan, David Kung, Ruchir Puri, Lakshmi N. Reddy, Michael A. Kazda, "An Integrated Environment for Technology Closure of Deep-Submicron IC Designs," IEEE Design and Test of Computers, vol. 21, no. 1, pp. 14-22, January/February, 2004.
 
 
BibTex
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@article{ 10.1109/MDT.2004.1261846,
author = {Louise Trevillyan and David Kung and Ruchir Puri and Lakshmi N. Reddy and Michael A. Kazda},
title = {An Integrated Environment for Technology Closure of Deep-Submicron IC Designs},
journal ={IEEE Design and Test of Computers},
volume = {21},
number = {1},
issn = {0740-7475},
year = {2004},
pages = {14-22},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.1261846},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - An Integrated Environment for Technology Closure of Deep-Submicron IC Designs
IS - 1
SN - 0740-7475
SP14
EP22
EPD - 14-22
A1 - Louise Trevillyan,
A1 - David Kung,
A1 - Ruchir Puri,
A1 - Lakshmi N. Reddy,
A1 - Michael A. Kazda,
PY - 2004
VL - 21
JA - IEEE Design and Test of Computers
ER -
 
Louise Trevillyan, IBM T.J. Watson Research Center
David Kung, IBM T.J. Watson Research Center
Ruchir Puri, IBM T.J. Watson Research Center
Lakshmi N. Reddy, IBM Microelectronics Division
Michael A. Kazda, IBM Microelectronics Division

With larger chip images and increasingly aggressive technologies, key design processes must interoperate. PDS, a physical-synthesis system, accomplishes technology closure through interacting processes of logic optimization, placement, timing, clock insertion, and routing, all using a common infrastructure with robust variable-accuracy analysis abstractions.

Citation:
Louise Trevillyan, David Kung, Ruchir Puri, Lakshmi N. Reddy, Michael A. Kazda, "An Integrated Environment for Technology Closure of Deep-Submicron IC Designs," IEEE Design and Test of Computers, vol. 21, no. 1, pp. 14-22, Jan./Feb. 2004, doi:10.1109/MDT.2004.1261846
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