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DFT for Delay Fault Testing of High-Performance Digital Circuits
May/June 2004 (vol. 21 no. 3)
pp. 248-258
ASCII Text
x 
 
Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi, "DFT for Delay Fault Testing of High-Performance Digital Circuits," IEEE Design and Test of Computers, vol. 21, no. 3, pp. 248-258, May/June, 2004.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2004.10,
author = {Bhaskar Chatterjee and Manoj Sachdev and Ali Keshavarzi},
title = {DFT for Delay Fault Testing of High-Performance Digital Circuits},
journal ={IEEE Design and Test of Computers},
volume = {21},
number = {3},
issn = {0740-7475},
year = {2004},
pages = {248-258},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.10},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - DFT for Delay Fault Testing of High-Performance Digital Circuits
IS - 3
SN - 0740-7475
SP248
EP258
EPD - 248-258
A1 - Bhaskar Chatterjee,
A1 - Manoj Sachdev,
A1 - Ali Keshavarzi,
PY - 2004
VL - 21
JA - IEEE Design and Test of Computers
ER -
 
Bhaskar Chatterjee, University of Waterloo
Manoj Sachdev, University of Waterloo
Ali Keshavarzi, Intel Laboratories
Timing-only parametric defects are a major source of failures and test escapes in modern ICs. A DFT technique using compound domino logic gates with footer transistors uncovers these hard-to-detect defects with minimal performance and power overheads.
Citation:
Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi, "DFT for Delay Fault Testing of High-Performance Digital Circuits," IEEE Design and Test of Computers, vol. 21, no. 3, pp. 248-258, May/June 2004, doi:10.1109/MDT.2004.10
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