An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs

Design&Test
2003
Issue No. 1 - January/February
Abstract - An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs

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January/February 2003 (vol. 20 no. 1)

pp. 60-67

	ASCII Text	x
	Florence Aza?, Yves Bertrand, Michel Renovell, Andr? Ivanov, Sassan Tabatabaei, "An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs," IEEE Design and Test of Computers, vol. 20, no. 1, pp. 60-67, January/February, 2003.

	BibTex	x
	@article{ 10.1109/MDT.2003.1173054, author = {Florence Aza? and Yves Bertrand and Michel Renovell and Andr? Ivanov and Sassan Tabatabaei}, title = {An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs}, journal ={IEEE Design and Test of Computers}, volume = {20}, number = {1}, issn = {0740-7475}, year = {2003}, pages = {60-67}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1173054}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs IS - 1 SN - 0740-7475 SP60 EP67 EPD - 60-67 A1 - Florence Aza?, A1 - Yves Bertrand, A1 - Michel Renovell, A1 - Andr? Ivanov, A1 - Sassan Tabatabaei, PY - 2003 VL - 20 JA - IEEE Design and Test of Computers ER -

Florence Aza?, LIRMM, University of Montpellier

Yves Bertrand, LIRMM, University of Montpellier

Michel Renovell, LIRMM, University of Montpellier

Andr? Ivanov, University of British Columbia

Sassan Tabatabaei, University of British Columbia

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1173054

Traditional functional testing of mixed-signal ICs is slow and requires costly, dedicated test equipment. The authors update the standard PLL architecture to allow simple digital testing. The all-digital strategy yields catastrophic fault coverage as high as that of the classical functional test, plus it is fast, extremely simple to implement, and requires only standard digital test equipment.

Citation:

Florence Aza?, Yves Bertrand, Michel Renovell, Andr? Ivanov, Sassan Tabatabaei, "An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs," IEEE Design and Test of Computers, vol. 20, no. 1, pp. 60-67, Jan./Feb. 2003, doi:10.1109/MDT.2003.1173054

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