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A Methodology for Synthesis of Data Path Circuitse
November/December 2002 (vol. 19 no. 6)
pp. 90-100
ASCII Text
x 
 
Amit Chowdhary, Rajesh Gupta, "A Methodology for Synthesis of Data Path Circuitse," IEEE Design and Test of Computers, vol. 19, no. 6, pp. 90-100, November/December, 2002.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2002.1047748,
author = {Amit Chowdhary and Rajesh Gupta},
title = {A Methodology for Synthesis of Data Path Circuitse},
journal ={IEEE Design and Test of Computers},
volume = {19},
number = {6},
issn = {0740-7475},
year = {2002},
pages = {90-100},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2002.1047748},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - A Methodology for Synthesis of Data Path Circuitse
IS - 6
SN - 0740-7475
SP90
EP100
EPD - 90-100
A1 - Amit Chowdhary,
A1 - Rajesh Gupta,
PY - 2002
VL - 19
JA - IEEE Design and Test of Computers
ER -
 

This methodology extracts the regularity of data path blocks from their HDL descriptions and preserves it throughout the synthesis process. By automating various design steps, the methodology significantly improves design productivity and achieves designs comparable in terms of delay and size to manually designed circuits.

Citation:
Amit Chowdhary, Rajesh Gupta, "A Methodology for Synthesis of Data Path Circuitse," IEEE Design and Test of Computers, vol. 19, no. 6, pp. 90-100, Nov./Dec. 2002, doi:10.1109/MDT.2002.1047748
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