Efficient Sequential Test Generation Based on Logic Simulation
September/October 2002 (vol. 19 no. 5)
pp. 56-64
ASCII Text
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Shuo Sheng, Michael S. Hsiao,
"Efficient Sequential Test Generation Based on Logic Simulation,"
IEEE Design and Test of Computers, vol. 19, no. 5, pp. 56-64, September/October, 2002.
BibTex
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@article{
10.1109/MDT.2002.1033793, author = {Shuo Sheng and Michael S. Hsiao}, title = {Efficient Sequential Test Generation Based on Logic Simulation}, journal ={IEEE Design and Test of Computers}, volume = {19}, number = {5}, issn = {0740-7475}, year = {2002}, pages = {56-64}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2002.1033793}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
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TY - MGZN JO - IEEE Design and Test of Computers TI - Efficient Sequential Test Generation Based on Logic Simulation IS - 5 SN - 0740-7475 SP56 EP64 EPD - 56-64 A1 - Shuo Sheng, A1 - Michael S. Hsiao, PY - 2002 VL - 19 JA - IEEE Design and Test of Computers ER -
A simple and highly efficient logic-simulation-based test generator uses a genetic algorithm to achieve both high fault coverage and short test generation times.
Citation:
Shuo Sheng, Michael S. Hsiao, "Efficient Sequential Test Generation Based on Logic Simulation," IEEE Design and Test of Computers, vol. 19, no. 5, pp. 56-64, Sep./Oct. 2002, doi:10.1109/MDT.2002.1033793
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