Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits

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September/October 2002 (vol. 19 no. 5)

pp. 36-43

	ASCII Text	x
	Ali Keshavarzi, James W. Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins, "Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits," IEEE Design and Test of Computers, vol. 19, no. 5, pp. 36-43, September/October, 2002.

	BibTex	x
	@article{ 10.1109/MDT.2002.1033790, author = {Ali Keshavarzi and James W. Tschanz and Siva Narendra and Vivek De and W. Robert Daasch and Kaushik Roy and Manoj Sachdev and Charles F. Hawkins}, title = {Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits}, journal ={IEEE Design and Test of Computers}, volume = {19}, number = {5}, issn = {0740-7475}, year = {2002}, pages = {36-43}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2002.1033790}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits IS - 5 SN - 0740-7475 SP36 EP43 EPD - 36-43 A1 - Ali Keshavarzi, A1 - James W. Tschanz, A1 - Siva Narendra, A1 - Vivek De, A1 - W. Robert Daasch, A1 - Kaushik Roy, A1 - Manoj Sachdev, A1 - Charles F. Hawkins, PY - 2002 VL - 19 JA - IEEE Design and Test of Computers ER -

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2002.1033790

Barriers to technology scaling, such as leakage and parameter variations, challenge the effectiveness of current-based test techniques. This correlative multi-parameter test approach improves current testing sensitivity, exploiting dependencies of transistor and circuit leakage on operating frequency, temperature, and body bias to discriminate fast but intrinsically leaky ICs from defective ones.

Citation:

Ali Keshavarzi, James W. Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins, "Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits," IEEE Design and Test of Computers, vol. 19, no. 5, pp. 36-43, Sep./Oct. 2002, doi:10.1109/MDT.2002.1033790

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