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IP for Embedded Diagnosis
May/June 2002 (vol. 19 no. 3)
pp. 46-55
ASCII Text
x 
 
Stephen Pateras, "IP for Embedded Diagnosis," IEEE Design and Test of Computers, vol. 19, no. 3, pp. 46-55, May/June, 2002.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2002.1003795,
author = {Stephen Pateras},
title = {IP for Embedded Diagnosis},
journal ={IEEE Design and Test of Computers},
volume = {19},
number = {3},
issn = {0740-7475},
year = {2002},
pages = {46-55},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2002.1003795},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - IP for Embedded Diagnosis
IS - 3
SN - 0740-7475
SP46
EP55
EPD - 46-55
A1 - Stephen Pateras,
PY - 2002
VL - 19
JA - IEEE Design and Test of Computers
ER -
 

An integrated BIST-based flow streamlines debugging and fault diagnosis of increasingly complex SoC devices. This methodology can help meet the requirement for shorter time to market.

Citation:
Stephen Pateras, "IP for Embedded Diagnosis," IEEE Design and Test of Computers, vol. 19, no. 3, pp. 46-55, May/June 2002, doi:10.1109/MDT.2002.1003795
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