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Design for Debug: Catching Design Errors in Digital Chips
May/June 2002 (vol. 19 no. 3)
pp. 37-45
ASCII Text
x 
 
Bart Vermeulen, Sandeep Kumar Goel, "Design for Debug: Catching Design Errors in Digital Chips," IEEE Design and Test of Computers, vol. 19, no. 3, pp. 37-45, May/June, 2002.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2002.1003792,
author = {Bart Vermeulen and Sandeep Kumar Goel},
title = {Design for Debug: Catching Design Errors in Digital Chips},
journal ={IEEE Design and Test of Computers},
volume = {19},
number = {3},
issn = {0740-7475},
year = {2002},
pages = {37-45},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2002.1003792},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Design for Debug: Catching Design Errors in Digital Chips
IS - 3
SN - 0740-7475
SP37
EP45
EPD - 37-45
A1 - Bart Vermeulen,
A1 - Sandeep Kumar Goel,
PY - 2002
VL - 19
JA - IEEE Design and Test of Computers
ER -
 

For large, complex ICs, engineers need efficient techniques for debugging first silicon. The system presented here consists of an on-chip debug infrastructure and supporting debugger software,which interacts with the infrastructure to make the chip's features accessible through a serial interface.

Citation:
Bart Vermeulen, Sandeep Kumar Goel, "Design for Debug: Catching Design Errors in Digital Chips," IEEE Design and Test of Computers, vol. 19, no. 3, pp. 37-45, May/June 2002, doi:10.1109/MDT.2002.1003792
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