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Embedded Timing Analysis: A SoC Infrastructure
May/June 2002 (vol. 19 no. 3)
pp. 24-36
ASCII Text
x 
 
Sassan Tabatabaei, André Ivanov, "Embedded Timing Analysis: A SoC Infrastructure," IEEE Design and Test of Computers, vol. 19, no. 3, pp. 24-36, May/June, 2002.
 
 
BibTex
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@article{ 10.1109/MDT.2002.1003786,
author = {Sassan Tabatabaei and André Ivanov},
title = {Embedded Timing Analysis: A SoC Infrastructure},
journal ={IEEE Design and Test of Computers},
volume = {19},
number = {3},
issn = {0740-7475},
year = {2002},
pages = {24-36},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2002.1003786},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Embedded Timing Analysis: A SoC Infrastructure
IS - 3
SN - 0740-7475
SP24
EP36
EPD - 24-36
A1 - Sassan Tabatabaei,
A1 - André Ivanov,
PY - 2002
VL - 19
JA - IEEE Design and Test of Computers
ER -
 

This SoC infrastructure core is a flexible, scalable, and highly accurate embedded time interval analyzer (ETIA), used to measure a variety of timing-related SoC characteristics, including jitter. The ETIA requires little design and area overhead and performs accurately under process and environment variation and noise.

Citation:
Sassan Tabatabaei, André Ivanov, "Embedded Timing Analysis: A SoC Infrastructure," IEEE Design and Test of Computers, vol. 19, no. 3, pp. 24-36, May/June 2002, doi:10.1109/MDT.2002.1003786
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