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Embracing and Extending 20th-Century Instruction Set Architectures
April 2007 (vol. 40 no. 4)
pp. 68-75
ASCII Text
x 
 
Joe Gebis, David Patterson, "Embracing and Extending 20th-Century Instruction Set Architectures," Computer, vol. 40, no. 4, pp. 68-75, April, 2007.
 
 
BibTex
x
 
@article{ 10.1109/MC.2007.124,
author = {Joe Gebis and David Patterson},
title = {Embracing and Extending 20th-Century Instruction Set Architectures},
journal ={Computer},
volume = {40},
number = {4},
issn = {0018-9162},
year = {2007},
pages = {68-75},
doi = {http://doi.ieeecomputersociety.org/10.1109/MC.2007.124},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - Computer
TI - Embracing and Extending 20th-Century Instruction Set Architectures
IS - 4
SN - 0018-9162
SP68
EP75
EPD - 68-75
A1 - Joe Gebis,
A1 - David Patterson,
PY - 2007
KW - instruction set architectures
KW - PowerPC
KW - vector architecture
KW - SIMD processors
VL - 40
JA - Computer
ER -
 
Joe Gebis, University of California, Berkeley
David Patterson, University of California, Berkeley
A vector case study shows how new functionality can be added to extend the 80x86 and PowerPC architectures to support a full vector architecture, primarily by enhancing their multimedia extensions to provide a better model for compilers and an easier-to-understand model for programmers.
Index Terms:
instruction set architectures, PowerPC, vector architecture, SIMD processors
Citation:
Joe Gebis, David Patterson, "Embracing and Extending 20th-Century Instruction Set Architectures," Computer, vol. 40, no. 4, pp. 68-75, Apr. 2007, doi:10.1109/MC.2007.124
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