Programming Models for Hybrid CPU/FPGA Chips

Computer
2004
Issue No. 1 - January
Abstract - Programming Models for Hybrid CPU/FPGA Chips

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January 2004 (vol. 37 no. 1)

pp. 118-120

	ASCII Text	x
	David Andrews, Douglas Niehaus, Peter Ashenden, "Programming Models for Hybrid CPU/FPGA Chips," Computer, vol. 37, no. 1, pp. 118-120, January, 2004.

	BibTex	x
	@article{ 10.1109/MC.2004.1260732, author = {David Andrews and Douglas Niehaus and Peter Ashenden}, title = {Programming Models for Hybrid CPU/FPGA Chips}, journal ={Computer}, volume = {37}, number = {1}, issn = {0018-9162}, year = {2004}, pages = {118-120}, doi = {http://doi.ieeecomputersociety.org/10.1109/MC.2004.1260732}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - Computer TI - Programming Models for Hybrid CPU/FPGA Chips IS - 1 SN - 0018-9162 SP118 EP120 EPD - 118-120 A1 - David Andrews, A1 - Douglas Niehaus, A1 - Peter Ashenden, PY - 2004 VL - 37 JA - Computer ER -

David Andrews, University of Kansas

Douglas Niehaus, University of Kansas

Peter Ashenden, Ashenden Designs

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MC.2004.1260732

Components that combine a CPU and reconfigurable logic gates need a programming model that abstracts the computational hardware.

Citation:

David Andrews, Douglas Niehaus, Peter Ashenden, "Programming Models for Hybrid CPU/FPGA Chips," Computer, vol. 37, no. 1, pp. 118-120, Jan. 2004, doi:10.1109/MC.2004.1260732

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