Billion-Transistor Architectures

Computer
1997
Issue No. 9 - September
Abstract - Billion-Transistor Architectures

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September 1997 (vol. 30 no. 9)

pp. 46-49

	ASCII Text	x
	Doug Burger, James R. Goodman, "Billion-Transistor Architectures," Computer, vol. 30, no. 9, pp. 46-49, September, 1997.

	BibTex	x
	@article{ 10.1109/MC.1997.612248, author = {Doug Burger and James R. Goodman}, title = {Billion-Transistor Architectures}, journal ={Computer}, volume = {30}, number = {9}, issn = {0018-9162}, year = {1997}, pages = {46-49}, doi = {http://doi.ieeecomputersociety.org/10.1109/MC.1997.612248}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - Computer TI - Billion-Transistor Architectures IS - 9 SN - 0018-9162 SP46 EP49 EPD - 46-49 A1 - Doug Burger, A1 - James R. Goodman, PY - 1997 VL - 30 JA - Computer ER -

Doug Burger

James R. Goodman

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MC.1997.612248

Advances in semiconductor manufacturing will permit an unprecedented number of transistors on a single processor die. But what architecture will make the best use of these riches?

Citation:

Doug Burger, James R. Goodman, "Billion-Transistor Architectures," Computer, vol. 30, no. 9, pp. 46-49, Sept. 1997, doi:10.1109/MC.1997.612248

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