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13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
Parallel Logic Simulation of Million-Gate VLSI Circuits
Atlanta, Georgia
September 27-September 29
ISBN: 0-7695-2458-3
ASCII Text
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Lijuan Zhu, Gilbert Chen, Boleslaw K. Szymanski, Carl Tropper, Tong Zhang, "Parallel Logic Simulation of Million-Gate VLSI Circuits," Modeling, Analysis, and Simulation of Computer Systems, International Symposium on, pp. 521-524, 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 2005.
 
 
BibTex
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@article{ 10.1109/MASCOT.2005.49,
author = {Lijuan Zhu and Gilbert Chen and Boleslaw K. Szymanski and Carl Tropper and Tong Zhang},
title = {Parallel Logic Simulation of Million-Gate VLSI Circuits},
journal ={Modeling, Analysis, and Simulation of Computer Systems, International Symposium on},
volume = {0},
year = {2005},
issn = {1526-7539},
pages = {521-524},
doi = {http://doi.ieeecomputersociety.org/10.1109/MASCOT.2005.49},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Modeling, Analysis, and Simulation of Computer Systems, International Symposium on
TI - Parallel Logic Simulation of Million-Gate VLSI Circuits
SN - 1526-7539
SP521
EP524
A1 - Lijuan Zhu,
A1 - Gilbert Chen,
A1 - Boleslaw K. Szymanski,
A1 - Carl Tropper,
A1 - Tong Zhang,
PY - 2005
KW - null
VL - 0
JA - Modeling, Analysis, and Simulation of Computer Systems, International Symposium on
ER -
 
Lijuan Zhu, Rensselaer Polytechnic Institute, Computer Science Department
Gilbert Chen, Rensselaer Polytechnic Institute, Computer Science Department
Boleslaw K. Szymanski, Rensselaer Polytechnic Institute, Computer Science Department
Carl Tropper, McGill University, School of Computer Science
Tong Zhang, Rensselaer Polytechnic Institute, ECSE

The complexity of today?s VLSI chip designs makes veri fication a necessary step before fabrication. As a result, gate-level logic simulation has became an integral component of the VLSI circuit design process which verifies the design and analyzes its behavior. Since the designs constantly grow in size and complexity, there is a need for ever more ef?cient simulations to keep the gate-level logic veri- fication time acceptably small.

The focus of this paper is an efficient simulation of large chip designs. We present the design and implementation of a new parallel simulator, called DSIM, and demonstrate DSIM?s efficiency and speed by simulating a million gate circuit using different numbers of processors.

Citation:
Lijuan Zhu, Gilbert Chen, Boleslaw K. Szymanski, Carl Tropper, Tong Zhang, "Parallel Logic Simulation of Million-Gate VLSI Circuits," mascots, pp.521-524, 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 2005
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