IEEE John Vincent Atanasoff 2006 International Symposium on Modern Computing (JVA'06)
A Parallel Architecture for Radix-2 Fast Fourier Transform
Sofia, Bulgari
October 03-October 06
ISBN: 0-7695-2643-8
DOI Bookmark:
http://doi.ieeecomputersociety.org/10.1109/JVA.2006.4
This paper describes the main problems, connected with the parallel implementation of the Fast Fourier Transform (FFT) algorithm on different highperformance computer architectures. Discussed is a possibility for the FFT parallel realization on a parallel architecture, suitable for implementation on field programmable gate arrays (FPGA) and based on perfect shuffle interconnection pattern. Discussed are the main properties of the architecture and similarities with the scalar case Analyzed are the problems of parameterization and automatic generation of the architecture.
Index Terms:
Parallel Fast Fourier Transform, Highperformance computer architectures.
Citation:
Ph. Philipov, V. Lazarov, Z. Zlatev, M. Ivanova, "A Parallel Architecture for Radix-2 Fast Fourier Transform," jva, pp.229-234, IEEE John Vincent Atanasoff 2006 International Symposium on Modern Computing (JVA'06), 2006
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