Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) PLL-Based Fractional-N Frequency Synthesizers Banff, Alberta, Canada July 20-July 24 ISBN: 0-7695-2403-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.91
Recent trends in the commercial use of fractional-N frequency synthesis can be attributed to the characteristic of independent loop bandwidth-channel spacing that results in low phase noise and relaxes the Phase-Locked Loop (PLL) design constraints. This paper reviews several techniques used to implement fractional-N frequency synthesizers and discusses the advantages and disadvantages. It also addresses design options and associated trade-offs.
Citation:
Farhad Zarkeshvari, Peter Noel, Tad Kwasniewski, "PLL-Based Fractional-N Frequency Synthesizers," iwsoc, pp.85-91, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||