loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)
Orthogonalized Communication Architecture for MP-SoC with Global Bus
Banff, Alberta, Canada
July 20-July 24
ISBN: 0-7695-2403-6
Jin Lee, Information and Communications University
Sin-Chong Park, Information and Communications University
In platform based SoC design, the computational part and communication part of the system are required to be orthogonalized. In this paper, we propose the fully orthogonalized communication architecture of multi-processor SoC (MP-SoC) which has a global bus architecture. In order to orthognalize communication and computation, we use the central arbiter which not only performs arbitration of transactions, but generates of transaction information. Each master has a transactor which translate the information from the central arbiter, so that the master doesn?t need to synchronize with other processors. This paper also provides the transaction level modeling(TLM) methodology at timed functional (TF) level with SystemC 2.0.1 and Master-Slave Library.
Citation:
Jin Lee, Sin-Chong Park, "Orthogonalized Communication Architecture for MP-SoC with Global Bus," iwsoc, pp.541-545, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005
Usage of this product signifies your acceptance of the Terms of Use.