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Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)
Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process
Banff, Alberta, Canada
July 20-July 24
ISBN: 0-7695-2403-6
ASCII Text
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Kwang-Jow Gan, Dong-Shong Liang, Chung-Chih Hsiao, Shih-Yu Wang, Feng-Chang Chiang, Cher-Shiung Tsai, Yaw-Hwang Chen, Shun-Huo Kuo, Chi-Pin Chen, "Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process," System-on-Chip for Real-Time Applications, International Workshop on, pp. 392-395, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005.
 
 
BibTex
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@article{ 10.1109/IWSOC.2005.80,
author = {Kwang-Jow Gan and Dong-Shong Liang and Chung-Chih Hsiao and Shih-Yu Wang and Feng-Chang Chiang and Cher-Shiung Tsai and Yaw-Hwang Chen and Shun-Huo Kuo and Chi-Pin Chen},
title = {Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process},
journal ={System-on-Chip for Real-Time Applications, International Workshop on},
volume = {0},
year = {2005},
isbn = {0-7695-2403-6},
pages = {392-395},
doi = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.80},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - System-on-Chip for Real-Time Applications, International Workshop on
TI - Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process
SN - 0-7695-2403-6
SP392
EP395
A1 - Kwang-Jow Gan,
A1 - Dong-Shong Liang,
A1 - Chung-Chih Hsiao,
A1 - Shih-Yu Wang,
A1 - Feng-Chang Chiang,
A1 - Cher-Shiung Tsai,
A1 - Yaw-Hwang Chen,
A1 - Shun-Huo Kuo,
A1 - Chi-Pin Chen,
PY - 2005
KW - null
VL - 0
JA - System-on-Chip for Real-Time Applications, International Workshop on
ER -
 
Kwang-Jow Gan, Kun Shan University of Technology
Dong-Shong Liang, Kun Shan University of Technology
Chung-Chih Hsiao, Kun Shan University of Technology
Shih-Yu Wang, Kun Shan University of Technology
Feng-Chang Chiang, Kun Shan University of Technology
Cher-Shiung Tsai, Kun Shan University of Technology
Yaw-Hwang Chen, Kun Shan University of Technology
Shun-Huo Kuo, Kun Shan University of Technology
Chi-Pin Chen, Kun Shan University of Technology
We propose a new MOS-NDR device that is composed of the metal-oxide-semiconductor field-effect-transistor (MOS) devices. This device could exhibit the negative differential resistance (NDR) characteristics in the current-voltage characteristics by suitably modulating the MOS parameters. We design a logic circuit which can operate the inverter, NOR, and NAND gates. The devices and circuits are fabricated by the standard 0.35?m CMOS process.
Citation:
Kwang-Jow Gan, Dong-Shong Liang, Chung-Chih Hsiao, Shih-Yu Wang, Feng-Chang Chiang, Cher-Shiung Tsai, Yaw-Hwang Chen, Shun-Huo Kuo, Chi-Pin Chen, "Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process," iwsoc, pp.392-395, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005
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