The dramatic increase in leakage current coupled with the large increase in variability in highly scaled CMOS technologies, pose a major challenge for future IC design. Leakage variability can not be neglected anymore, due to the increase of leakage power percentage in modern ICs. In this paper, the main sources of variations and how they impact leakage current are discussed. Design guidelines to reduce variability based on several leakage reduction techniques are also presented. It is shown that reverse body bias technique increases leakage variability due to its deteriorating effect on Drain-Induced Barrier Lowering (DIBL). This paper highlights the need for further efforts in the area of statistical leakage estimation, as well as variation tolerant circuit techniques.