Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Instruction Based Testbench Architecture, invited Banff, Alberta, Canada July 20-July 24 ISBN: 0-7695-2403-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.76
This paper presents the synthesizable test-bench architecture based on the defined instruction for standalone mode verification. The proposed test-bench performs fast emulation with low resource and increases flexibility and reusability with variable description of instructions. To prove the performance of our testbench, we verified IEEE 802.11a PHY baseband system and compare with co-sim mode and modified co-sim mode emulation.
Citation:
Ho-seok Choi, Seung-beom Lee, Sin-chong Park, "Instruction Based Testbench Architecture, invited," iwsoc, pp.329-333, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||