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Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)
Instruction Based Testbench Architecture, invited
Banff, Alberta, Canada
July 20-July 24
ISBN: 0-7695-2403-6
Ho-seok Choi, Information and Communications University
Seung-beom Lee, Information and Communications University
Sin-chong Park, Information and Communications University
This paper presents the synthesizable test-bench architecture based on the defined instruction for standalone mode verification. The proposed test-bench performs fast emulation with low resource and increases flexibility and reusability with variable description of instructions. To prove the performance of our testbench, we verified IEEE 802.11a PHY baseband system and compare with co-sim mode and modified co-sim mode emulation.
Citation:
Ho-seok Choi, Seung-beom Lee, Sin-chong Park, "Instruction Based Testbench Architecture, invited," iwsoc, pp.329-333, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005
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