Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite Optimization

I
IWSOC
2005
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)
Abstract - Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite Optimization

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Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)

Banff, Alberta, Canada

July 20-July 24

ISBN: 0-7695-2403-6

	ASCII Text	x
	P. L. Takouda, M. F. Anjos, A Vannelli, "Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite Optimization," System-on-Chip for Real-Time Applications, International Workshop on, pp. 275-280, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005.

	BibTex	x
	@article{ 10.1109/IWSOC.2005.69, author = {P. L. Takouda and M. F. Anjos and A Vannelli}, title = {Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite Optimization}, journal ={System-on-Chip for Real-Time Applications, International Workshop on}, volume = {0}, year = {2005}, isbn = {0-7695-2403-6}, pages = {275-280}, doi = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.69}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - System-on-Chip for Real-Time Applications, International Workshop on TI - Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite Optimization SN - 0-7695-2403-6 SP275 EP280 A1 - P. L. Takouda, A1 - M. F. Anjos, A1 - A Vannelli, PY - 2005 KW - null VL - 0 JA - System-on-Chip for Real-Time Applications, International Workshop on ER -

P. L. Takouda, University of Waterloo

M. F. Anjos, University of Waterloo

A Vannelli, University of Waterloo

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.69

We investigate the application of Semidefinite Programming (SDP) techniques to the VLSI macrocell floorplanning problem. We propose a new mixed-integer SDP formulation of the problem which leads to new SDP relaxations. This approach has been implemented and we report global lower bounds for some MCNC benchmark macrocell problems.

Citation:

P. L. Takouda, M. F. Anjos, A Vannelli, "Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite Optimization," iwsoc, pp.275-280, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005

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