loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)
Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits
Banff, Alberta, Canada
July 20-July 24
ISBN: 0-7695-2403-6
ASCII Text
x 
 
Dong-Shong Liang, Kwang-Jow Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang, "Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits," System-on-Chip for Real-Time Applications, International Workshop on, pp. 78-81, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005.
 
 
BibTex
x
 
@article{ 10.1109/IWSOC.2005.66,
author = {Dong-Shong Liang and Kwang-Jow Gan and Long-Xian Su and Chi-Pin Chen and Chung-Chih Hsiao and Cher Shiung Tsai and Yaw-Hwang Chen and Shih-Yu Wang and Shun-Huo Kuo and Feng-Chang Chiang},
title = {Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits},
journal ={System-on-Chip for Real-Time Applications, International Workshop on},
volume = {0},
year = {2005},
isbn = {0-7695-2403-6},
pages = {78-81},
doi = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.66},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - System-on-Chip for Real-Time Applications, International Workshop on
TI - Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits
SN - 0-7695-2403-6
SP78
EP81
A1 - Dong-Shong Liang,
A1 - Kwang-Jow Gan,
A1 - Long-Xian Su,
A1 - Chi-Pin Chen,
A1 - Chung-Chih Hsiao,
A1 - Cher Shiung Tsai,
A1 - Yaw-Hwang Chen,
A1 - Shih-Yu Wang,
A1 - Shun-Huo Kuo,
A1 - Feng-Chang Chiang,
PY - 2005
KW - null
VL - 0
JA - System-on-Chip for Real-Time Applications, International Workshop on
ER -
 
Dong-Shong Liang, Kun Shan University of Technology
Kwang-Jow Gan, Kun Shan University of Technology
Long-Xian Su, Kun Shan University of Technology
Chi-Pin Chen, Kun Shan University of Technology
Chung-Chih Hsiao, Kun Shan University of Technology
Cher Shiung Tsai, Kun Shan University of Technology
Yaw-Hwang Chen, Kun Shan University of Technology
Shih-Yu Wang, Kun Shan University of Technology
Shun-Huo Kuo, Kun Shan University of Technology
Feng-Chang Chiang, Kun Shan University of Technology
This paper describes the design of a four-valued memory cell based on a three-peak MOS-NDR circuit. We connect three MOS-NDR devices in parallel that can create a three-peak current-voltage curve by suitably arranging the parameters. Due to its folding IV characteristics, multiple -peak NDR device is a very promising device for multiple -valued logic application. This memory cell structure can be easily extended to implement more states in a memory circuit.
Citation:
Dong-Shong Liang, Kwang-Jow Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang, "Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits," iwsoc, pp.78-81, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005
Usage of this product signifies your acceptance of the Terms of Use.