Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) ESD-Induced Internal Core Device Failure: New Failure Modes in System-on-Chip (SoC) Designs, invited Banff, Alberta, Canada July 20-July 24 ISBN: 0-7695-2403-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.58
With MOSFET scaling, increased design complexity, and multiple system power domains, ESD failures occur in internal core areas which are not connected to external package pins. A review of the various internal core device failure mechanisms and design recommendations will be presented.
Citation:
Yoon Huh, Peter Bendix, Kyungjin Min, Jau-Wen Chen, Ravindra Narayan, Larry D. Johnson, Steven H. Voldman, "ESD-Induced Internal Core Device Failure: New Failure Modes in System-on-Chip (SoC) Designs, invited," iwsoc, pp.47-53, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||