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Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)
Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm
Banff, Alberta, Canada
July 20-July 24
ISBN: 0-7695-2403-6
ASCII Text
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N. Masoumi, M. Ahmadian, F. Raissi, M. Masoumi, J. Ghasemi, "Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm," System-on-Chip for Real-Time Applications, International Workshop on, pp. 283-288, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005.
 
 
BibTex
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@article{ 10.1109/IWSOC.2005.57,
author = {N. Masoumi and M. Ahmadian and F. Raissi and M. Masoumi and J. Ghasemi},
title = {Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm},
journal ={System-on-Chip for Real-Time Applications, International Workshop on},
volume = {0},
year = {2005},
isbn = {0-7695-2403-6},
pages = {283-288},
doi = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.57},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - System-on-Chip for Real-Time Applications, International Workshop on
TI - Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm
SN - 0-7695-2403-6
SP283
EP288
A1 - N. Masoumi,
A1 - M. Ahmadian,
A1 - F. Raissi,
A1 - M. Masoumi,
A1 - J. Ghasemi,
PY - 2005
KW - null
VL - 0
JA - System-on-Chip for Real-Time Applications, International Workshop on
ER -
 
N. Masoumi, University of Tehran
M. Ahmadian, K. N. Toosi University of Technology
F. Raissi, K. N. Toosi University of Technology
M. Masoumi, K. N. Toosi University of Technology
J. Ghasemi, University of Tehran
In this paper we describe a new algorithm for transistor sizing in CMOS DCVSL (Differential Cascode Voltage Switch Logic) digital circuits. Our proposed method has two different approaches with low computational burden, mathematical based and genetic algorithm based. Using our transistor sizing algorithm, we minimized the propagation delay of a DCVSL full-adder and a DCVSL XOR in 0.5 um CMOS technology. At first, the optimum sizes of these circuits were calculated to obtain the minimum propagation delay. Then the final transistor sizes were obtained by trading off speed, energy and area to meet a set of performance requirements.
Citation:
N. Masoumi, M. Ahmadian, F. Raissi, M. Masoumi, J. Ghasemi, "Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm," iwsoc, pp.283-288, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005
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