Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits Banff, Alberta, Canada July 20-July 24 ISBN: 0-7695-2403-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.49
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to low-voltage/low-power digital circuitry. The simulated power consumption of standard CMOS gates is compared to that of QFGMOS implementations in a 0.18?m process for different supply voltages and device sizes. A 0.4V VDD full-adder biased for propagation delay similar to that of 0.8V CMOS is simulated and shown to consume 1.2?W for a 50MHz input, representing more than a 50% power reduction over the CMOS equivalent. A divide-by-16 circuit designed for operation at a maximum frequency of 400MHz uses 25?W, 45?W, and 75?W for supplies of 0.4V, 0.6V and 0.8V.
Citation:
Kenneth A. Townsend, James W. Haslett, Krzysztof Iniewski, "Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits," iwsoc, pp.132-136, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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