An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking

I
IWSOC
2005
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)
Abstract - An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking

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	Similar Articles Articles by Mona Safar Articles by M. Watheq El-Kharashi Articles by Ashraf Salem

Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)

Banff, Alberta, Canada

July 20-July 24

ISBN: 0-7695-2403-6

	ASCII Text	x
	Mona Safar, M. Watheq El-Kharashi, Ashraf Salem, "An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking," System-on-Chip for Real-Time Applications, International Workshop on, pp. 419-424, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005.

	BibTex	x
	@article{ 10.1109/IWSOC.2005.40, author = {Mona Safar and M. Watheq El-Kharashi and Ashraf Salem}, title = {An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking}, journal ={System-on-Chip for Real-Time Applications, International Workshop on}, volume = {0}, year = {2005}, isbn = {0-7695-2403-6}, pages = {419-424}, doi = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.40}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - System-on-Chip for Real-Time Applications, International Workshop on TI - An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking SN - 0-7695-2403-6 SP419 EP424 A1 - Mona Safar, A1 - M. Watheq El-Kharashi, A1 - Ashraf Salem, PY - 2005 KW - null VL - 0 JA - System-on-Chip for Real-Time Applications, International Workshop on ER -

Mona Safar, Ain Shams University

M. Watheq El-Kharashi, University of Victoria

Ashraf Salem, Mentor Graphics

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.40

In this paper we present Software/Reconfigurable hardware SAT accelerator for Combinational Equivalence Checking. The SAT binary clauses are mapped into an implication graph and the ternary clauses are kept in an indexed clause database and mapped into the clause evaluator and conflict detector implemented on FPGA The validity of the proposed approach is shown through the ISCAS'85 benchmark circuits.

Citation:

Mona Safar, M. Watheq El-Kharashi, Ashraf Salem, "An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking," iwsoc, pp.419-424, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005

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