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Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)
An Automatic Layout Generator for I/O Cells
Banff, Alberta, Canada
July 20-July 24
ISBN: 0-7695-2403-6
Li-Chun Tien, Southern Taiwan University of Technology
Jing-Jou Tang, Southern Taiwan University of Technology
Mi-Chang Chang, Southern Taiwan University of Technology
We present a new design methodology for I/O cell library design automation. It?s different from the conventional cell library compilers or generators, which generate the cells for standard cells or regular structures (e.g., SRAM). The proposed compiler will generate I/O cells based on a set of parameterized unit-cells with the features of scalable geometry dependence. The compilation results of the I/O cells have been proved in a 0.13um LOGIC 1P8M process. Through this compiler, the number of unit-cells needed to be maintained is dramatically reduced, thereby reducing library development costs and time to market.
Citation:
Li-Chun Tien, Jing-Jou Tang, Mi-Chang Chang, "An Automatic Layout Generator for I/O Cells," iwsoc, pp.295-300, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005
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