Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) An Area-Reduced Scheme for Modulo 2ⁿ-1 Addition/Subtraction Banff, Alberta, Canada July 20-July 24 ISBN: 0-7695-2403-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.38
In this paper, we present a versatile area-reduced scheme for modulo 2ⁿ-1 adders and subtractors using a novel MUX-based increment/decrement algorithm. A FPGA-based comparison of the proposed modulo adder and the conventional modulo adder designs is carried out. The implementation results show that the proposed adder reduces the area close to 30% compared with the modulo adder of Bayoumi et al.. The delay and the power are also reduced around 10%. In addition, it is also shown that the proposed design requires less hardware resources than the parallel-prefix modulo adder of Kalampoukas et al. while providing a comparable operation speed.
Citation:
Shaoqiang Bi, Warren J. Gross, Wei Wang, Asim Al-Khalili, M. N. S. Swamy, "An Area-Reduced Scheme for Modulo 2ⁿ-1 Addition/Subtraction," iwsoc, pp.396-399, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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