Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) An Acoustic Echo Canceller Chip Banff, Alberta, Canada July 20-July 24 ISBN: 0-7695-2403-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.36
This paper has mentioned new algorithms in adaptive acoustic echo cancellation (AEC): Subband Adaptive Filtering (SAF) and Partitioned Block Hartley Domain Adaptive Filtering (PBHDAF). The computational complexity of these algorithms is less than their older partners with very fast convergence rate. We have proposed these algorithms for real time processing and we implement this system as acoustic echo canceller with Very high speed integrated circuit Hardware Description Language (VHDL). Also a block diagram for integrated implementation of this AEC is proposed that can be constructed in System On Chip (SOC) or System In Package (SIP) technologies.
Citation:
Mostafa Borhani, Vafa Sedghi, "An Acoustic Echo Canceller Chip," iwsoc, pp.193-198, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||