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Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)
A Precise Model for Leakage Power Estimation in VLSI Circuits
Banff, Alberta, Canada
July 20-July 24
ISBN: 0-7695-2403-6
ASCII Text
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J. Derakhshandeh, Nasser Masoumi, B. Kasiri, Y. Farazmand, Akbarzadeh, S. Aghnoot, "A Precise Model for Leakage Power Estimation in VLSI Circuits," System-on-Chip for Real-Time Applications, International Workshop on, pp. 337-340, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005.
 
 
BibTex
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@article{ 10.1109/IWSOC.2005.23,
author = {J. Derakhshandeh and Nasser Masoumi and B. Kasiri and Y. Farazmand and Akbarzadeh and S. Aghnoot},
title = {A Precise Model for Leakage Power Estimation in VLSI Circuits},
journal ={System-on-Chip for Real-Time Applications, International Workshop on},
volume = {0},
year = {2005},
isbn = {0-7695-2403-6},
pages = {337-340},
doi = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.23},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - System-on-Chip for Real-Time Applications, International Workshop on
TI - A Precise Model for Leakage Power Estimation in VLSI Circuits
SN - 0-7695-2403-6
SP337
EP340
A1 - J. Derakhshandeh,
A1 - Nasser Masoumi,
A1 - B. Kasiri,
A1 - Y. Farazmand,
A1 - Akbarzadeh,
A1 - S. Aghnoot,
PY - 2005
KW - null
VL - 0
JA - System-on-Chip for Real-Time Applications, International Workshop on
ER -
 
J. Derakhshandeh, University of Tehran
Nasser Masoumi, University of Tehran
B. Kasiri, University of Tehran
Y. Farazmand, University of Tehran
Akbarzadeh, University of Tehran
S. Aghnoot, University of Tehran
Leakage current is becoming very important factor in determining the feasibility of designs, today. Due to exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by a linear model. In the first model the inputs are the number of all gates that used in circuit. And in the second model inputs are the number of gates and in the third model inputs are the number of input states of gates. The model is validated for a large benchmark circuits and the leakage power predicted by our model is within 5% of the actual leakage power predicted by a popular tool used in the industry.
Citation:
J. Derakhshandeh, Nasser Masoumi, B. Kasiri, Y. Farazmand, Akbarzadeh, S. Aghnoot, "A Precise Model for Leakage Power Estimation in VLSI Circuits," iwsoc, pp.337-340, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005
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