Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) A 0.65V, 1.9mW CMOS Low-Noise Amplifier at 5GHz Banff, Alberta, Canada July 20-July 24 ISBN: 0-7695-2403-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.2
An ultra low-voltage (0.65 V), 5 GHz low noise amplifier (LNA) has been designed, laid out and simulated using Spectre simulator in a standard TSMC 0.18um CMOS technology. The proposed LNA achieves better performance than conventional cascode topology and are confirmed by simulation results. The LNA provides a high gain of 20 dB, a noise figure of 1.4 dB, power dissipation of 1.9 mW from a 0.65 V power supply. To the best of author?s knowledge this is the lowest voltage supply CMOS LNA design reported to date.
Citation:
Yanjie Wang, M. Zamin Khan, Kris Iniewski, "A 0.65V, 1.9mW CMOS Low-Noise Amplifier at 5GHz," iwsoc, pp.247-251, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||