This paper presents a new methodology for improving overall efficiency of class-E power amplifiers. Power amplifiers are designed for maximum efficiency at the highest output power, while the efficiency decreases as the output power reduces. To achieve a long battery life and block interference, output power must be controlled based on the distance between a transmitter and a receiver. This new methodology employs optimized circuit topology in power control circuit in order to have small drop in efficiency at low output power. The proposed circuit is simulated using Hspice in 0.25 pm CMOS technology as well as ADS lumped model of spiral inductors is employed. The results indicate that the efficiency reduces about 40% when the power amplifer operates at 10% of the maximum output power.