Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Very High Radix Scalable Montgomery Multipliers Banff, Alberta, Canada July 20-July 24 ISBN: 0-7695-2403-6
This paper describes a very high radix scalable Montgomery multiplier. It extends the radix-2 Tenca-Ko? scalable architecture using w ? v-bit integer multipliers in place of AND gates. The new design can perform 1024-bit modular exponentiation in 6.6 ms using 2847 4-input lookup tables and 32 16 x 16 multipliers, making it the fastest scalable design yet reported.
Citation:
Kyle Kelley, David Harris, "Very High Radix Scalable Montgomery Multipliers," iwsoc, pp.400-404, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||