UMHexagonS Algorithm Based Motion Estimation Architecture for H.264/AVC

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	Similar Articles Articles by Choudhury A. Rahman Articles by Wael Badawy

Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)

Banff, Alberta, Canada

July 20-July 24

ISBN: 0-7695-2403-6

	ASCII Text	x
	Choudhury A. Rahman, Wael Badawy, "UMHexagonS Algorithm Based Motion Estimation Architecture for H.264/AVC," System-on-Chip for Real-Time Applications, International Workshop on, pp. 207-210, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005.

	BibTex	x
	@article{ 10.1109/IWSOC.2005.110, author = {Choudhury A. Rahman and Wael Badawy}, title = {UMHexagonS Algorithm Based Motion Estimation Architecture for H.264/AVC}, journal ={System-on-Chip for Real-Time Applications, International Workshop on}, volume = {0}, year = {2005}, isbn = {0-7695-2403-6}, pages = {207-210}, doi = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.110}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - System-on-Chip for Real-Time Applications, International Workshop on TI - UMHexagonS Algorithm Based Motion Estimation Architecture for H.264/AVC SN - 0-7695-2403-6 SP207 EP210 A1 - Choudhury A. Rahman, A1 - Wael Badawy, PY - 2005 KW - null VL - 0 JA - System-on-Chip for Real-Time Applications, International Workshop on ER -

Choudhury A. Rahman, University of Calgary

Wael Badawy, University of Calgary

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.110

This paper presents an integer pel variable block motion estimation architecture based on JVT accepted UMHexagonS algorithm for H.264/MPEG-4 Part 10 (AVC) encoder. The proposed pipelined architecture is capable of calculating the required 41 motion vectors of various size blocks supported by H.264/AVC within a 16x16 block in parallel. The architecture can be used for rapid prototyping of motion estimation core using FPGA. The performance analysis shows that the architecture is capable of processing CIF frame sequences in real time considering 5 reference frames within the search range of ?16 at a clock speed of around 30 MHz.

Citation:

Choudhury A. Rahman, Wael Badawy, "UMHexagonS Algorithm Based Motion Estimation Architecture for H.264/AVC," iwsoc, pp.207-210, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005

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