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Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)
Transaction Analysis of Multiprocessor Based Platform with Bus Matrix
Banff, Alberta, Canada
July 20-July 24
ISBN: 0-7695-2403-6
Seungbeom Lee, Information and Communications University
Sin-Chong Park, Information and Communications University
This paper presents an analysis of transaction of multiprocessor platform with bus matrix. Simple equations about the latency and throughput for this architecture are derived. From this equation we evaluate operating frequency to meet latency and throughput requirements. This architecture is modeled as transaction level model (TLM) in SystemC in order to confirm the validation of the governing equation. The result of simulation corresponds to that of the derived equation.
Citation:
Seungbeom Lee, Sin-Chong Park, "Transaction Analysis of Multiprocessor Based Platform with Bus Matrix," iwsoc, pp.552-556, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005
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