With ever-finer device geometry, increasing device counts and interconnect delays playing a larger role in the performance of a system on a chip, the architectures that are used to support such technologies must take these factors into account. Highly pipelined or highly parallel architectures that utilize local processing, and therefore shorter interconnects, are required. Three-dimensional, monolithic integrated circuit technology which can significantly shorten the interconnects and accommodate more devices per chip may be an attractive solution. The basic idea is presented along with an illustrative application specific processor design.