Deep submicron technologies are causing interconnect delays to become a larger fraction of the clock cycle time. A solution to this problem is to pipeline the long wire in order to increase channel throughput and maintain an acceptable clock frequency. The delay of the interconnect is distributed over several clock cycles by inserting relay stations which allow for fully synchronous operation at a higher frequency. We discuss a relay station scheme that takes advantage of storage in the interconnect to minimize system stalls. We also discuss various implementation issues and design choices, such as clock gating. Additionally, we will present the results of a system-on-chip crossbar, which we designed to utilize these modules. We believe that this type of approach is crucial for maintaining the overall improvement of performance in future systems and technologies.