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The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03)
Design, Simulation and Implementation of a Low-Power Digital Decimation Filter for G.232 Standard
Calgary, Alberta, Canada
June 30-July 02
ISBN: 0-7695-1944-X
ASCII Text
x 
 
Nikzad Babaii, Abdolreza Nabavi, "Design, Simulation and Implementation of a Low-Power Digital Decimation Filter for G.232 Standard," System-on-Chip for Real-Time Applications, International Workshop on, pp. 390, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003.
 
 
BibTex
x
 
@article{ 10.1109/IWSOC.2003.1213068,
author = {Nikzad Babaii and Abdolreza Nabavi},
title = {Design, Simulation and Implementation of a Low-Power Digital Decimation Filter for G.232 Standard},
journal ={System-on-Chip for Real-Time Applications, International Workshop on},
volume = {0},
year = {2003},
isbn = {0-7695-1944-X},
pages = {390},
doi = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2003.1213068},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - System-on-Chip for Real-Time Applications, International Workshop on
TI - Design, Simulation and Implementation of a Low-Power Digital Decimation Filter for G.232 Standard
SN - 0-7695-1944-X
SP
EP
A1 - Nikzad Babaii,
A1 - Abdolreza Nabavi,
PY - 2003
KW - null
VL - 0
JA - System-on-Chip for Real-Time Applications, International Workshop on
ER -
 
Nikzad Babaii, Tarbiat Modarres University,
Abdolreza Nabavi, Tarbiat Modarres University
A power efficient multistage digital decimation filter for an ADSL modem is presented. In this design, a fractional delay (FD) filter with complex coefficients, a symmetric FIR filter, and a shift register are used to meet the requirements of the G.232 standard. The multistage architecture of the decimation filter consumes less than 28% of power consumed by single-stage implementation for oversampling ratio of 16. Although the order of the designed filter is low (16), it provides very accurate magnitude and group delay responses within the passband.
Citation:
Nikzad Babaii, Abdolreza Nabavi, "Design, Simulation and Implementation of a Low-Power Digital Decimation Filter for G.232 Standard," iwsoc, pp.390, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003
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