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The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03)
An Efficient Mechanism for Debugging RTL Description
Calgary, Alberta, Canada
June 30-July 02
ISBN: 0-7695-1944-X
Jiann-Chyi Rau, Department of Electrical Engineering, Tamkang University
Yi-Yuan Chang, Department of Electrical Engineering, Tamkang University
Chia-Hung Lin, Department of Electrical Engineering, Tamkang University
In this paper, an efficient algorithm to diagnose design errors in RTL description is proposed. The diagnosis algorithm exploits the hierarchy available in RTL designs to locate design errors. Using data-path to reduce the number of error candidates and ensure that true errors are included in. According to the estimated probability, the most suspected error candidates would be reported first in the display. The advantages of the proposed method are simple and available.
Citation:
Jiann-Chyi Rau, Yi-Yuan Chang, Chia-Hung Lin, "An Efficient Mechanism for Debugging RTL Description," iwsoc, pp.370, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003
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