Chang Hee Pyoun, Chi Ho Lin, Hi Seok Kim, Jong Wha Chong, "THE EFFICIENT BUS ARBITRATION SCHEME IN SOC ENVIRONMENT," System-on-Chip for Real-Time Applications, International Workshop on, pp. 311, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003.

@article{ 10.1109/IWSOC.2003.1213054,
author = {Chang Hee Pyoun and Chi Ho Lin and Hi Seok Kim and Jong Wha Chong},
title = {THE EFFICIENT BUS ARBITRATION SCHEME IN SOC ENVIRONMENT},
journal ={System-on-Chip for Real-Time Applications, International Workshop on},
volume = {0},
year = {2003},
isbn = {0-7695-1944-X},
pages = {311},
doi = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2003.1213054},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}

TY - CONF
JO - System-on-Chip for Real-Time Applications, International Workshop on
TI - THE EFFICIENT BUS ARBITRATION SCHEME IN SOC ENVIRONMENT
SN - 0-7695-1944-X
SP
EP
A1 - Chang Hee Pyoun,
A1 - Chi Ho Lin,
A1 - Hi Seok Kim,
A1 - Jong Wha Chong,
PY - 2003
KW - This paper presents the dynamic bus arbiter architecture for a system on chip design. The conventional bus-distribution algorithms
KW - such as the static fixed priority and the round robin
KW - show several defects that are bus starvation
KW - and low system performance because of bus distribution latency in a bus cycle time. The proposed dynamic bus architecture is based on a probability bus distribution algorithm and uses an adaptive ticket value method to solve the impartiality and starvation problems. The simulation results show that the proposed algorithm reduces the buffer size of a master by 11% and decreases the bus request latency of a master by 50%.
VL - 0
JA - System-on-Chip for Real-Time Applications, International Workshop on
ER -