System on Chip (SoC) design in the forthcoming billion-transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks. The success of this approach depends on the seamless integration of cores like processors, memories, UARTs, etc. Some of the main problems in future SoC designs arise from non scalable global wire delays, failure to achieve global synchronization, errors due to signal integrity issues and difficulties associated with non scalable bus-based functional interconnects. These problems can be addressed by using a network-centric approach to design SoCs, where instead of global wiring, IP blocks are integrated using a switch-based on-chip interconnection network. One of the major concerns with interconnection networks is throughput degradation due to idle physical channels. By introducing the concept of virtual channels in an on-chip interconnection network, the overall throughput of the SoC can be improved. To achieve this throughput improvement, extra silicon area is required but the overall area consumed by the switches can be made to amount to a very small portion of a billiontransistor SoC.