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The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03)
Pullpipelining: A technique for systolic pipelined circuits
Calgary, Alberta, Canada
June 30-July 02
ISBN: 0-7695-1944-X
ASCII Text
x 
 
Oswaldo Cadenas, Graham Megson, "Pullpipelining: A technique for systolic pipelined circuits," System-on-Chip for Real-Time Applications, International Workshop on, pp. 205, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003.
 
 
BibTex
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@article{ 10.1109/IWSOC.2003.1213036,
author = {Oswaldo Cadenas and Graham Megson},
title = {Pullpipelining: A technique for systolic pipelined circuits},
journal ={System-on-Chip for Real-Time Applications, International Workshop on},
volume = {0},
year = {2003},
isbn = {0-7695-1944-X},
pages = {205},
doi = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2003.1213036},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - System-on-Chip for Real-Time Applications, International Workshop on
TI - Pullpipelining: A technique for systolic pipelined circuits
SN - 0-7695-1944-X
SP
EP
A1 - Oswaldo Cadenas,
A1 - Graham Megson,
PY - 2003
KW - null
VL - 0
JA - System-on-Chip for Real-Time Applications, International Workshop on
ER -
 
Oswaldo Cadenas, University of Reading, School of Systems Engineering,
Graham Megson, University of Reading, School of Systems Engineering,
Pullpipelining, a pipeline technique where data is pulled from successor stages from predecessor stages is proposed. Control circuits using a synchronous, a semisynchronous and an asynchronous approach are given. Simulation examples for a DLX generic RISC datapath show that common control pipeline circuit overhead is avoided using the proposal. Applications to linear systolic arrays in cases when computation is finished at early stages in the array are foreseen. This would allow run-time data-driven digital frequency modulation of synchronous pipelined designs. This has applications to implement algorithms exhibiting average-case processing time using a synchronous approach.
Citation:
Oswaldo Cadenas, Graham Megson, "Pullpipelining: A technique for systolic pipelined circuits," iwsoc, pp.205, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003
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