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The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03)
Evaluating Template-Based Instruction Compression on Transport Triggered Architectures
Calgary, Alberta, Canada
June 30-July 02
ISBN: 0-7695-1944-X
ASCII Text
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Jari Heikkinen, Tommi Rantanen, Andrea Cilio, Jarmo Takala, Henk Corporaal, "Evaluating Template-Based Instruction Compression on Transport Triggered Architectures," System-on-Chip for Real-Time Applications, International Workshop on, pp. 192, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003.
 
 
BibTex
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@article{ 10.1109/IWSOC.2003.1213033,
author = {Jari Heikkinen and Tommi Rantanen and Andrea Cilio and Jarmo Takala and Henk Corporaal},
title = {Evaluating Template-Based Instruction Compression on Transport Triggered Architectures},
journal ={System-on-Chip for Real-Time Applications, International Workshop on},
volume = {0},
year = {2003},
isbn = {0-7695-1944-X},
pages = {192},
doi = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2003.1213033},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - System-on-Chip for Real-Time Applications, International Workshop on
TI - Evaluating Template-Based Instruction Compression on Transport Triggered Architectures
SN - 0-7695-1944-X
SP
EP
A1 - Jari Heikkinen,
A1 - Tommi Rantanen,
A1 - Andrea Cilio,
A1 - Jarmo Takala,
A1 - Henk Corporaal,
PY - 2003
KW - null
VL - 0
JA - System-on-Chip for Real-Time Applications, International Workshop on
ER -
 
Jari Heikkinen, Tampere University of Technology
Tommi Rantanen, Tampere University of Technology
Andrea Cilio, Tampere University of Technology
Jarmo Takala, Tampere University of Technology
Henk Corporaal, Eindhoven University of Technology
Program code size has become a critical design constraint of embedded systems. Code compression is one of the approaches to reduce the program code size; it results in smaller memories and reduced cost of the chip. In this paper, a code compression method based on instruction templates has been used to improve the code density transport triggered architecture. Six applications taken from different application domains are used for benchmarking. The obtained results show significant improvements in code density.
Citation:
Jari Heikkinen, Tommi Rantanen, Andrea Cilio, Jarmo Takala, Henk Corporaal, "Evaluating Template-Based Instruction Compression on Transport Triggered Architectures," iwsoc, pp.192, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003
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