FEASIBILITY OF FIXED-POINT TRANSVERSAL ADAPTIVE FILTERS IN FPGA DEVICES WITH EMBEDDED DSP BLOCKS

I
IWSOC
2003
The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03)
Abstract - FEASIBILITY OF FIXED-POINT TRANSVERSAL ADAPTIVE FILTERS IN FPGA DEVICES WITH EMBEDDED DSP BLOCKS

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The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03)

Calgary, Alberta, Canada

June 30-July 02

ISBN: 0-7695-1944-X

	ASCII Text	x
	Andrew Y. Lin, Karl S. G ugel, Jos? C. Pr?ncipe, "FEASIBILITY OF FIXED-POINT TRANSVERSAL ADAPTIVE FILTERS IN FPGA DEVICES WITH EMBEDDED DSP BLOCKS," System-on-Chip for Real-Time Applications, International Workshop on, pp. 157, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003.

	BibTex	x
	@article{ 10.1109/IWSOC.2003.1213026, author = {Andrew Y. Lin and Karl S. G ugel and Jos? C. Pr?ncipe}, title = {FEASIBILITY OF FIXED-POINT TRANSVERSAL ADAPTIVE FILTERS IN FPGA DEVICES WITH EMBEDDED DSP BLOCKS}, journal ={System-on-Chip for Real-Time Applications, International Workshop on}, volume = {0}, year = {2003}, isbn = {0-7695-1944-X}, pages = {157}, doi = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2003.1213026}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - System-on-Chip for Real-Time Applications, International Workshop on TI - FEASIBILITY OF FIXED-POINT TRANSVERSAL ADAPTIVE FILTERS IN FPGA DEVICES WITH EMBEDDED DSP BLOCKS SN - 0-7695-1944-X SP EP A1 - Andrew Y. Lin, A1 - Karl S. G ugel, A1 - Jos? C. Pr?ncipe, PY - 2003 KW - null VL - 0 JA - System-on-Chip for Real-Time Applications, International Workshop on ER -

Andrew Y. Lin, Computational NeuroEngineering Laboratory, Dept. of ECE, University of Florida

Karl S. G ugel, Computational NeuroEngineering Laboratory, Dept. of ECE, University of Florida

Jos? C. Pr?ncipe, Computational NeuroEngineering Laboratory, Dept. of ECE, University of Florida

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWSOC.2003.1213026

Transversal adaptive filters for digital signal processing have traditionally been implemented into DSP processors due to their ability to perform fast floating-point arithmetic. However, with its growing die size as well as incorporating the embedded DSP block, the FPGA devices have become a serious contender in the signal processing market. Although it is not yet feasible to use floating-point arithmetic in modern FPGAs, it is sufficient to use fixed-point arithmetic and still achieve tap-weight convergence for adaptive filters. This paper examines the feasibility of implementing an adaptive algorithm, namely the LMS algorithm, based on fixed-point arithmetic, using the Altera Stratix device.

Citation:

Andrew Y. Lin, Karl S. G ugel, Jos? C. Pr?ncipe, "FEASIBILITY OF FIXED-POINT TRANSVERSAL ADAPTIVE FILTERS IN FPGA DEVICES WITH EMBEDDED DSP BLOCKS," iwsoc, pp.157, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003

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