The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03)
The Design of Low-Power Fixed-Point FIR Differentiator IP Blocks
Calgary, Alberta, Canada
June 30-July 02
ISBN: 0-7695-1944-X
This paper presents a method for the generation of Lowpower Finite duration Impulse Response (FIR) lowpass differentiator Intellectual Property (IP) blocks. The design problem is formulated as a discrete constrained Optimization problem where the total squared frequency Response approximation error is minimized subject to constraints on the power consumption and frequency response approximation error. It is demonstrated that the power consumption can be reduced while still satisfying the frequency response specifications.
Citation:
T.W. Fox, A. Carreira, L.E. Turner, "The Design of Low-Power Fixed-Point FIR Differentiator IP Blocks," iwsoc, pp.53, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003
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