Increasing demands created by Systems-On-Chip (SOC) and process advances have increased the difficulty of timing driven placement. The primary issue in SOC is timing closure. This requires us to look at timing at all design levels, especially placement. Recently, several promising approaches for timing-driven placement have been presented using net length constraints for timing optimization [1, 2]. A Net Length Constraint (NLC) is an upper limit on a net?s length. These net-constrained global placement techniques give excellent timing results by meeting NLCs on timing-critical nets. These works focused only on global NLC placement. Detailed placement and legalization are important steps in the placement flow. Current algorithms, which are not NLC aware, give back the gains from global NLC placement. The contributions of this paper are a new NLC global placement rebalancing method and two detailed placement algorithms that work in conjunction with the recursive bisection net-constrained global placer [1]. The first detailed placer uses gridbased placement and transportation solving to assign instances to the grid. The second detailed placer uses simulated annealing to optimize placement for NLC. On benchmark circuits from MCNC and Intel Corporation, the grid and simulated annealing placers are able to achieve placements which exceed constraints by, on average, only 2.7% and 1.9%, respectively.